February 14, 2025

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Hardware-efficient preparation of architecture-specific graph states on near-term quantum computers

Hardware-efficient preparation of architecture-specific graph states on near-term quantum computers

Our compilation method is based on a formal model that considers the graph state structure, topology, and error characterization of a given quantum computer to yield an improved graph state preparation circuit. The improved graph state preparation circuit is compiled while considering gate commutation relations, gate cancellations, and accurate timing information provided by the quantum computing operator.

Figure 2 depicts the individual steps of the developed quantum circuit compilation method for graph state preparation. First, the structure of a graph state and the current error characterization are used to determine the placement of the graph state qubits onto the physical qubits of the target quantum computer. This step is realized by methods such as mapomatic32 that consider the product of current gate fidelities on the quantum computer to determine an improved placement.

Then, the placement information is used together with the structure of a given graph state, accurate quantum gate timing information, and an objective function to inform the generation of a formal model. The formal model can then be solved to yield an optimized graph state preparation circuit33. The formal model consists of variables representing valid preparation circuits if the value assignments of the model variables satisfy the constraints defined in this model. The solver then optimizes the valid assignment to the model variables with respect to given objective functions. The resulting assignment is provably optimal, i.e., the solver always finds the global minimum33.

Fig. 2
figure 2

Individual steps of the developed graph state preparation compilation method.

The compilation method assumes native graph states as defined in Section 3 and a target quantum computer with a basis gate set that includes CNOT and Hadamard gates. The CZ quantum gate needed in the construction of graph states is thus represented in this basis gate set by applying Hadamard gates before and after a CNOT gate on the CNOT’s target qubit for the remainder of this work34. Notably, the steps in this work focus on the currently available IBM quantum computers, where the CNOT gate is available natively, and the Hadamard gate is available through other single-qubit gates. The method developed in this work can be adapted for different basis gate sets35.

Model variables

The developed model has the following model variables for a graph state with quantum gates \(G=F\cup H\), where F is the set of two-qubit quantum gates, and H is the set of Hadamard gates in the graph state preparation circuit:

  • C — the set of Boolean variables representing the two different directions of CNOT gates. As the only two-qubit quantum gates in graph states are originally CZ quantum gates, the role of the target qubit and the control qubit is exchangeable, i.e., the direction of a CNOT can be set arbitrarily. The direction of CNOT gates has a significant impact on the duration of the CNOT gate26 and also affects how many quantum gates in the quantum circuit can be canceled.

  • S — the set of real variables representing the start times of each quantum gate in the graph state preparation circuit. The set of variables \(S_H\) represents the start times of Hadamard gates, and \(S_F\) represents the start times of CNOT gates with \(S = S_H \cup S_F\).

  • T — the set of real variables representing the end time of each quantum gate in the graph state preparation circuit. As above, the set of variables \(T_H\) represents the end times of Hadamard gates, and \(T_F\) represents the end times of CNOT gates with \(T = T_H \cup T_F\).

  • B — the set of Boolean variables indicating whether a Hadamard gate is canceled due to a directly subsequent or preceding Hadamard gate. In the native graph states considered in this work, there is no pair of two-qubit quantum gates on the same set of qubits. Therefore, only Hadamard gates can cancel out.

In addition, let \(H_f\) be the set of Hadamard quantum gates that transform the two-qubit quantum gate \(f\in F\) into the CZ quantum gate with \(H_f = H_f^- \cup H_f^+\), where \(H_f^-\) are single-qubit quantum gates occurring before and \(H_f^+\) are single-qubit quantum gates occurring after the computation of the two-qubit quantum gate f. For the IBM quantum computers considered in this work, the sets \(H_f^-\) and \(H_f^+\) consist of only one Hadamard gate each that is applied to the target qubit of the CNOT gate. The solver software used in this work33 can address the real variables in sets T and S. Alternatively, these real-valued variables can be discretized36.

Model constraints

Model constraints guarantee that a satisfying assignment to the model variables yields a valid quantum circuit. For the native graph state preparation circuits considered in this work, the constraints must assign the accurate duration to gates in the circuit, cancel Hadamard gates in the correct situations, and ensure the correct order of non-commuting quantum gates while allowing an arbitrary order of commuting quantum gates. First, the duration of the quantum gates in the graph state preparation quantum circuit is modeled depending on the chosen direction and the accurate timing information specified by the quantum computer vendor.

$$\beginaligned T_g – S_g = \left( d_g \wedge C_g\right) \vee \left( d’_g \wedge \lnot C_g \right) , \endaligned$$

(5)

for a two-qubit quantum gate g that has a gate duration of \(d_g\) in the direction \(C_g\) and \(d_g’\) in the other direction. The equations for a single-qubit quantum gate \(g’\) are similar but do not have a direction and, as such, are directly assigned their gate duration \(d_g’\) according to the difference of \(T_g’\) and \(S_g’\).

Next, the temporal order of quantum gates must be considered in a valid graph state preparation quantum circuit. In general, CZ quantum gates commute with each other, so the temporal order of these quantum gates can be set arbitrarily as long as a qubit is not participating in two CZ quantum gates at once34. Thus, as the CZ gate is represented by a CNOT gate and two Hadamard gates on the target qubit, the set of CNOT and corresponding Hadamard gates also commute with each other. Furthermore, two subsequent Hadamard gates cancel each other out.

The following equations capture the exact timings of Hadamard gates and CNOT gates. First, the timing of the CNOT gate f with the sandwiched Hadamard gates is fixed by:

$$\beginaligned T_h \le S_f, \forall h\in H_f^-, \endaligned$$

(6)

and

$$\beginaligned S_h \ge T_f, \forall h\in H_f^+. \endaligned$$

(7)

Note that the temporal order of quantum gates inside the sets \(H_i\) does not need to be fixed in our case because they consist of only one gate. Furthermore, we distinguish two cases of two quantum gates f and \(f’\) overlapping on the same qubit. First, if the control qubit or the target qubit of the quantum gates f and \(f’\) overlap, then

$$\beginaligned \left( T_f \le S_f’\right) \vee \left( S_f \ge T_f’\right) \endaligned$$

(8)

must hold, i.e., gate f must end before gate \(f’\) or gate f must start after gate \(f’\). In this case, the Hadamard gate on the target qubit of the CNOT gate cancels with the Hadamard gate h. Thus, the single-qubit quantum gates \(H_f\) associated with a two-qubit quantum gate f can overlap temporally with the computation of a different two-qubit quantum gate \(f’\) or its single-qubit quantum gates \(H_f’\). A conflicting temporal assignment of quantum gates, i.e., one qubit would need to participate in multiple quantum gates at once, can occur for gates that cancel. This is reflected through variables B that indicate which quantum gates are canceled, making the assigned computation time irrelevant.

Likewise, the following set of equations is enforced if the control qubit of quantum gate f overlaps with the target qubit of quantum gate \(f’\):

$$\beginaligned \left( T_f \le S_h^- \right) \vee \left( S_f \ge T_h^+\right) , h^-\in H_f’^-, h^+ \in H_f’^+. \endaligned$$

(9)

As Hadamard gates do not commute with CNOT gates, these equations limit the temporal placement of Hadamard gates to a preceding or a succeeding CNOT gate \(f’\) that is overlapping with gate f. In addition, the computation time of the CNOT gate cannot overlap with the computation time of a Hadamard gate.

The cancellation of Hadamard gates can be expressed by

$$\beginaligned B_h = \left( S_f \le S_h \right) \wedge \left( T_h \le T_f \right) , \endaligned$$

(10)

i.e., a Hadamard gate h is canceled if its computation time overlaps with a two-qubit quantum gate f whose target qubit occurs on the same qubit as the Hadamard gate h. Further domain constraints are omitted, e.g., restricting the start and end times to non-negative reals.

Objective functions

We develop four objective functions for the compilation of hardware-efficient graph state preparation quantum circuits. The first objective to achieve is to minimize the number of Hadamard gates along with the required CNOT gates for the preparation of a given native graph state. This is realized by maximizing the number of gate cancellations:

$$\beginaligned \max \sum B_i. \endaligned$$

(11)

In addition, reducing the effect of decoherence can be achieved by minimizing the overall duration of the graph state preparation circuit25. The duration of a quantum circuit can be minimized through

$$\beginaligned \min \mathcal T \text with \mathcal T \ge T_g, \forall g\in F\cup H, \endaligned$$

(12)

where \(T_g\) is the individual end time of the quantum gate g and \(\mathcal T\) is an auxiliary variable.

An additional figure of merit for reducing the impact of decoherence is maximizing the ’remaining’ coherence time on a qubit as given by the difference between the determined qubit coherence time and the circuit duration on each qubit. The remaining coherence time can be expressed by

$$\beginaligned \max M, \text with M \le D_q – \mathcal T_q, \endaligned$$

(13)

where \(D_q\) is the coherence time on qubit q and \(\mathcal T_q\) is the end time of the last quantum gate on qubit q. The variable \(\mathcal T_q\) can be determined analogously to Eq. (12).

The objective function concerns the reduction of crosstalk errors that occur when a two-qubit quantum gate is performed on a pair of qubits where neighboring qubits are not idle37,38,39. These types of context-dependent errors can have a large impact on the fidelity of quantum state preparation and thus pose a potential for minimization by

$$\beginaligned \left( T_g \le S_g’\right) \vee \left( S_g \ge T_g’\right) \endaligned$$

(14)

for all quantum gates g and \(g’\) where the quantum gate \(g’\) acts on neighboring qubits. These can be determined, e.g., by the methods introduced in Ref.38.

Deriving a quantum circuit from a solved formal model

A graph state preparation quantum circuit is exactly determined by the variables introduced in Section 4.1. The time and qubits of a quantum gate in the graph state preparation circuit are exactly fixed by the developed formal model, i.e., a quantum circuit representation can be derived in linear time by inspecting the model variable assignments.

A satisfiability modulo theories (SMT) solver such as the Z3 SMT solver can determine an assignment to these model variables that satisfies the constraints specified in Eq. (5) to (10) and is optimal with respect to a specified objective function such as defined in Eq. (11) to (14)33.

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